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ltc 4353 1 4353f typical a pplica t ion fea t ures descrip t ion dual low voltage ideal diode controller the lt c ? 4353 controls external n-channel mosfets to implement an ideal diode function. it replaces two high power schottky diodes and their associated heat sinks, saving power and board area. the ideal diode function permits low loss power supply oring and supply holdup applications. the ltc4353 regulates the forward-voltage drop across the mosfet to ensure smooth current transfer in diode- or applications. a fast turn-on reduces the load voltage droop during supply switchover. if the input supply fails or is shorted, a fast turn-off minimizes reverse-current transients. the controller operates with supplies from 2.9 v to 18 v. if both supplies are below 2.9 v, an external supply is needed at the v cc pin. enable inputs can be used to turn off the mosfet and put the controller in a low current state. status outputs indicate whether the mosfets are on or off. 2.9v to 18v, 10a ideal diode-or output maintained with failing input supply a pplica t ions n low loss replacement for power diodes n controls n-channel mosfets n 0v to 18v supply oring or holdup n 1 s gate turn-on and turn-off time n enable inputs n mosfet on-status outputs n 16-lead msop and dfn (4mm 3mm) packages n redundant power supplies n supply holdup n high availability systems and servers n telecom and network infrastructure l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap, powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7920013 and 8022679. si4126dy si4126dy gate1 cpo1 cpo2 gnd en1 en2 4353 ta01a 2.9v to 18v 2.9v to 18v *optional for fast turn-on 0.1f v out 10a 56nf* 56nf* v in1 v cc onst1 onst2 out1 out2 mosfet on-status outputs gate2 v in2 ltc4353 5s/div voltage 2v/div 4353 ta01b v in1 = 5.2v v in2 = 5v i l = 8a c l = 100f v in1 v in2 v out
ltc 4353 2 4353f a bsolu t e maxi m u m r a t ings v in 1 , v in 2 , out 1, out 2 voltages ................... ?2 v to 24 v v cc voltage ............................................... ? 0.3 v to 6.5 v gate 1, gate 2 voltages ( note 3) ............... ? 0.3 v to 34 v cpo 1, cpo 2 voltages ( note 3) ................... ? 0.3 v to 34 v en 1 , en 2 , onst 1 , onst 2 voltages ............. ? 0.3 v to 24 v cpo 1, cpo 2 average current ................................. 10 ma o nst 1 , onst 2 currents ........................................... 5 ma (notes 1, 2) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4353cde#pbf ltc4353cde#trpbf 4353 16-pin (4mm 3mm) plastic dfn 0c to 70c ltc4353ide#pbf ltc4353ide#trpbf 4353 16-pin (4mm 3mm) plastic dfn C40c to 85c ltc4353cms#pbf ltc4353cms#trpbf 4353 16-pin plastic msop 0c to 70c ltc4353ims#pbf ltc4353ims#trpbf 4353 16-pin plastic msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 en1 gnd v cc v in1 gate1 cpo1 out1 onst1 en2 nc nc v in2 gate2 cpo2 out2 onst2 top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 17) pcb gnd connection optional 1 2 3 4 5 6 7 8 en2 nc nc v in2 gate2 cpo2 out2 onst2 16 15 14 13 12 11 10 9 en1 gnd v cc v in1 gate1 cpo1 out1 onst1 top view ms package 16-lead plastic msop t jmax = 125c, ja = 125c/w p in c on f igura t ion operating ambient temperature range ltc 4 353 c ................................................ 0 c to 70 c ltc 4 353 i ............................................. ? 40 c to 85 c storage temperature range .................. ? 65 c to 150 c lead temperature ( soldering , 10 sec ) ms p ackage ...................................................... 30 0 c
ltc 4353 3 4353f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. symbol parameter conditions min typ max units supplies v in v in1 , v in2 operating range with external v cc supply l l 2.9 0 18 v cc v v v cc(ext) v cc external supply operating range v in1 , v in2 v cc l 2.9 6 v v cc(reg) v cc regulated voltage l 4.5 5 5.5 v i in v in1 , v in2 current enabled, higher supply enabled, lower supply pull-up disabled other v in = 11.7v, both en = 0v other v in = 12.3v, both en = 0v both v in = 0v, v cc = 5v, both en = 0v both en = 1v l l l l 1.5 200 C45 75 2.5 300 C80 160 ma a a a i cc v cc current enabled disabled v cc = 5v, both v in = 1.2v, both en = 0v v cc = 5v, both v in = 1.2v, both en = 1v l l 1.5 88 2.2 190 ma a v cc(uvlo) v cc undervoltage lockout threshold v cc rising l 2.3 2.55 2.7 v v cc(hyst) v cc undervoltage lockout hysteresis l 40 120 300 mv ideal diode control v fr forward regulation voltage (v in ? out) v in = 1.2v, v cc = 5v v in = 12v l l 2 2 12 25 25 50 mv mv v gate mosfet gate drive (gate C v in ) v fwd = 0.2v; i = 0, ?1a; highest v in =12v v fwd = 0.2v; i = 0, ?1a; highest v in =2.9v l l 10 4.5 12 7 14 9 v v t on(gate) gate1, gate2 turn-on propagation delay v fwd (= v in C out) step: ?0.3v to 0.3v l 0.4 1 s t off(gate) gate1, gate2 turn-off propagation delay v fwd step: 0.3v to ?0.3v l 0.3 1 s i gate gate1, gate2 fast pull-up current gate1, gate2 fast pull-down current gate1, gate2 off pull-down current v fwd = 0.4v, v gate = 0v, cpo = 17v v fwd = ?0.8v, v gate = 5v corresponding en = 1v, v gate = 2.5v l l l C0.9 0.9 65 C1.4 1.4 110 C1.9 1.9 160 a a a input/output pins v en(th) en1, en2 threshold voltage en falling l 580 600 620 mv v en(th) en1, en2 threshold hysteresis l 2 8 20 mv i en en1, en2 current at 0.6v l 0 1 a i out out1, out2 current enabled disabled out n = 0v, 12v; both en = 0v both en = 1v l l C4 8 160 16 a a i cpo(up) cpo1, cpo2 pull-up current cpo = v in l C40 C70 C115 a v ol onst1, onst2 output low voltage i = 1ma i = 3ma l l 0.14 0.42 0.4 1.2 v v v oh onst1, onst2 output high voltage i = ?1a l v cc C 1.4 v cc C 0.9 v cc C 0.5 v i onst onst1, onst2 leakage current at 12v l 0 1 a v gate(on) mosfet on-detect threshold (gate C v in ) onst pulls low l 0.28 0.7 1.1 v the l denotes those specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. note 3: internal clamps limit the gate and cpo pins to a minimum of 10v above, and a diode below the corresponding v in pin. driving these pins to voltages beyond the clamp may damage the device.
ltc 4353 4 4353f t a = 25c, v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. typical p er f or m ance c harac t eris t ics out current vs voltage forward regulation voltage vs v in voltage with external v cc ?v gate voltage vs current ?v gate and v cc voltages vs v in voltage onst output low voltage vs current onst output high voltage vs current v in current vs voltage v in current vs voltage with external v cc v cc current vs voltage v in (v) 0 ?0.5 0 1.5 3 6 129 15 0.5 2.0 1.0 2.5 18 4353 g01 i in (ma) other v in = 0v other v in = 12v v in (v) 4353 g02 i in (a) 0 0 150 250 1 2 43 5 50 ?50 100 200 6 v cc = 6v other v in = 0v 0 0.25 1.00 1.75 0.50 1.25 0.75 1.50 4353 g03 v cc (v) 0 1 2 43 5 6 i cc (ma) both v in = 0v 4 14 0 6 2 10 12 8 v in (v) 0 63 9 1512 18 4353 g07 v cc v gate ? v in , v cc (v) ?v gate v in (v) 0 0 15 30 1 2 43 5 20 10 25 5 4353 g05 v cc = 5v v fr (mv) v cc = 3.3v v out (v) 4353 g04 i out (a) 0 0 150 250 3 6 129 15 50 ?50 100 200 18 i gate (a) 0 ?20 ?40 ?80?60 ?100 ?120 4353 g06 v gate ? v in (v) v in = 18v ?2 0 2 8 14 4 10 6 12 out = v in ? 0.1v v in = 2.9v i onst (ma) 0 0 600 1 2 43 800 200 400 5 4353 g08 v ol (mv) i onst (a) 0 0 3 ?2 ?4 ?8?6 5 1 4 2 ?10 4353 g09 v oh (v)
ltc 4353 5 4353f t a = 25c, v in1 = v in2 = 12v, out = v in , v cc open, unless otherwise noted. typical p er f or m ance c harac t eris t ics start-up waveform on v in1 power-up fast gate switchover from failing supply p in func t ions cpo1, cpo2: charge pump output. connect a capacitor from this pin to the corresponding v in pin. the value of this capacitor should be approximately 10 the gate ca- pacitance (c iss ) of the mosfet switch. the charge stored on this capacitor is used to pull-up the gate during a fast turn-on. leave this pin open if fast turn-on is not needed. en1, en2: enable input. keep this pin below 0.6 v to en- able diode control on the corresponding supply. driving this pin high shuts off the mosfet gate ( current can still flow through its body diode). the comparator has a built- in hysteresis of 8 mv. having both en pins high lowers the current consumption of the controller. exposed pad ( de package only): this pin may be left open or connected to device ground. gate1, gate2: mosfet gate drive output. connect this pin to the gate of the external n-channel mosfet switch. an internal clamp limits the gate voltage to 12 v above, and a diode below the input supply. during fast turn-on, a 1.4a pull-up current charges gate from cpo. during fast turn-off, a 1.4 a pull-down current discharges ga te to v in . gnd: device ground. onst1, onst2: mosfet status output. this pin is pulled low by an internal switch when gate is more than 0.7v above v in to indicate an on mosfet. an internal 500k resistor pulls this pin up to a diode below v cc . it may be pulled above v cc using an external pull-up. tie to gnd or leave open if unused. out1, out2: output voltage sense input. connect this pin to the load side of the mosfet. the voltage sensed at this pin is used to control the mosfet gate. v cc : low voltage supply. connect a 0.1 f capacitor from this pin to ground. for v in 2.9 v, this pin provides decou- pling for an internal regulator that generates a 5 v supply. for applications where both v in < 2.9 v, also connect an external supply voltage in the 2.9 v to 6 v range to this pin. v in1 , v in2 : voltage sense and supply input. connect this pin to the supply side of the mosfet. the low volt- age supply v cc is generated from the higher of v in1 and v in2 . the voltage sensed at this pin is used to control the mosfet gate. 5ms/div voltage 5v/div 4353 g10 v in1 v cc out cpo1 cpo2 gate1 5s/div 4353 g11 ?v gate2 10v/div ?v gate1 5v/div v in2 2v/div v in1 2v/div v in1 = 5.2v v in2 = 5v c l = 100f i l = 8a
ltc 4353 6 4353f func t ional diagra m 4353 bd charge pump1 f = 3mhz ldo charge pump2 f = 3mhz *de package only gate1 off gate2 off ? + sa1 ? + ? + ? + ? + 11 cpo1 12 gate1 13 v in1 v fr1 v fr2 v cc v cc low gate1 v in2 v in1 10 9 8 out1 onst1 500k cp4 cp2 cp1 cp3 0.7v 0.6v 0.6v 2.55v v in1 cpo2 gate2 17 exposed pad* gnd v in2 out2 ? + ? + v cc gate2 onst2 500k cp5 0.7v v in2 disable1 disable2 1 en2 14 v cc 16 en1 z 6 5 15 4 7 + ? + ? + ? + ? sa2
ltc 4353 7 4353f o pera t ion the ltc4353 controls n-channel mosfets to emulate two ideal diodes. when enabled, each servo amplifier (sa1, sa2) controls the gate of the external mosfet to servo its forward voltage drop ( v fwd = v in C out) to v fr . the gate voltage rises to enhance the mosfet if the load current causes the drop to exceed v fr . for large output currents, the mosfet gate is driven fully on and the volt- age drop is equal to i fet ? r ds(on) . in the case of an input supply short-circuit, when the mosfet is conducting, a large reverse current starts flowing from the load towards the input. sa detects this failure condition as soon as it appears, and turns off the mosfet by rapidly pulling down its gate. sa quickly pulls up the gate whenever it senses a large for- ward voltage drop. an external capacitor between the cpo and v in pins is needed for fast gate pull-up. this capacitor is charged up, at device power-up, by the internal charge pump. the stored charge is used for the fast gate pull-up. the gate pin sources current from the cpo pin and sinks current to the v in and gnd pins. clamps limit the gate and cpo voltages to 12 v above and a diode below v in . internal switches pull the onst pins low when the gate to v in voltage exceeds 0.7 v to indicate that power is passing through the mosfet. ldo is a low dropout regulator that generates a 5 v supply at the v cc pin from the highest v in input. when both v in are below 2.9 v, an external supply in the 2.9 v to 6 v range is required at the v cc pin. v cc and en pin comparators, cp1 to cp3, control power passage. the mosfet is held off whenever the en pin is above 0.6 v, or the v cc pin is below 2.55 v. a high on both en pins lowers the current consumption of the device.
ltc 4353 8 4353f high availability systems often employ parallel connected power supplies or battery feeds to achieve redundancy and enhance system reliability. oring diodes have been a popular means of connecting these supplies at the point of load. diodes followed by storage capacitors also hold up supply voltages when an input voltage sags or has a brownout. the disadvantage of these approaches is the diodes significant forward-voltage drop and the result- ing power loss. the ltc4353 solves these problems by using an external n-channel mosfet as the pass element (see figure 1). the mosfet is turned on when power is being passed, allowing for a low voltage drop from the supply to the load. when the input source voltage drops below the output common supply voltage it turns off the mosfet, thereby matching the function and performance of an ideal diode. a pplica t ions i n f or m a t ion figure 1. 12v ideal diode-or with status lights figure 2. power supply configurations power supply configuration the ltc4353 can operate with input supplies down to 0v. this requires powering the v cc pin with an early external supply in the 2.9 v to 6 v range. in this range of operation v in should be lower than v cc . if v cc powers up after v in and backfeeding of v cc by the internal 5 v ldo is a concern, then a series resistor (few 100) or schottky diode limits device power dissipation and backfeeding of a low v cc supply when any v in is high. a 0.1 f bypass capacitor should also be connected between the v cc and gnd pins, close to the device. figure 2 illustrates this. if either v in operates above 2.9 v, the external supply at v cc is not needed. the 0.1 f capacitor is still required for bypassing. gate1 4353 f02 0v to v cc 0v to v cc v in1 v cc gate2 v in2 ltc4353 2.9v to 6v gate1 m1 m2 m1 m2 2.9v to 18v (0v to 18v) 0v to 18v (2.9v to 18v) v in1 v cc gate2 v in2 ltc4353 c vcc 0.1f c vcc 0.1f optional or here m1 si4126dy m2 si4126dy gate1 cpo1 cpo2 gnd en1 en2 4353 f01 12v 12v d1, d2: green led ln1351c c vcc 0.1f out 10a c1 56nf r1 2.7k c2 56nf v in1 v cc onst1 onst2 out1 out2 d1 d2 gate2 v in2 ltc4353 r2 2.7k c l
ltc 4353 9 4353f mosfet selection the ltc4353 drives n-channel mosfets to conduct the load current. the important features of the mosfet are its maximum drain-source voltage bv dss , maximum gate- source voltage v gs(max) , and the on-resistance r ds(on) . if an input is connected to ground, the full supply voltage can appear across the mosfet. to survive this, the bv dss must be higher than the supply voltages. the v gs(max) rating of the mosfet should exceed 14 v since that is the upper limit of the internal gate to v in clamp. the r ds( on) of the mosfet dictates the maximum voltage drop (i l ? r ds(on) ) and the power dissipated (i l 2 ? r ds(on) ) in the mosfet. note that the minimum mosfet voltage drop is controlled by the servo amplifier regulation volt- age, hence, picking a very low r ds(on) ( below v fr /i l ) may not be beneficial. cpo capacitor selection the recommended value of the capacitor between the cpo and v in pins is approximately 10 the input capacitance c iss of the mosfet. a larger capacitor takes a cor- respondingly longer time to be charged by the internal charge pump. a smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the mosfet gate capacitance. external cpo supply the internal charge pump takes milliseconds to charge up the cpo capacitor especially during device power-up. this time can be shortened by connecting an external supply to the cpo pin. a series resistor is needed to limit the current into the internal clamp between cpo and v in pins. the cpo supply should also be higher than the main input supply to meet the gate drive requirements of the mosfet. figure 3 shows such a 3.3 v ideal diode application, where a 12 v supply is connected to the cpo pins through a 1 k resistor. the 1 k limits the current into the cpo pin, when the v in pin is grounded. for the 8.7v gate drive (12v C 3.3 v), logic-level mosfets would be an appropriate choice for m1 and m2. input transient protection when the capacitances at the input and output are very small, rapid changes in current can cause transients that exceed the 24 v absolute maximum rating of the v in and out pins. in oring applications, one surge suppressor connected from out to ground clamps all the inputs. in the absence of a surge suppressor, an output capacitance of 10 f is sufficient in most applications to prevent the transient from exceeding 24v. figure 3. 3.3v ideal diode with external 12v supply powering cpo for faster start-up and refresh m1 m2 gate1 4353 f03 v ina 3.3v v inb 3.3v v in1 gate2 v in2 ltc4353 cpo1 cpo2 12v 1k 1k c1 56nf c2 56nf a pplica t ions i n f or m a t ion
ltc 4353 10 4353f figure 4. recommended pcb layout for m1, m2, c vcc a pplica t ions i n f or m a t ion design example the following design example demonstrates the calcula- tions involved for selecting components in a 12 v system with 10a maximum load current (see figure 1). first, calculate the r ds(on) of the mosfet to achieve the desired forward drop at full load. assuming a v drop of 30mv: r ds(on) v drop i load = 30mv 10a = 3m? the si4126dy offers a good solution in a so-8 sized package with a 2.8 m maximum r ds(on) , 30 v bv dss , and 20 v v gs(max) . the maximum power dissipation in the mosfet is: p = i 2 load ? r ds(on) = (10a) 2 ? 2.8m = 0.3w with a maximum steady-state thermal resistance ja of 35c/w, 0.3 w causes a modest 11 c rise in junction temperature of the si4126dy above the ambient. the input capacitance, c iss , of the si4126dy is about 5500pf. following the 10 recommendation, a 56nf capacitor is selected for c1 and c2. leds, d1 and d2, require around 3 ma for good luminous intensity. accounting for a 2 v diode drop and 0.6 v v ol , r1 and r2 are set to 2.7k. pcb layout considerations connect the v in and out pin traces as close as possible to the mosfets terminals. keep the traces to the mos- fet wide and short to minimize resistive losses. the pcb traces associated with the power path through the mosfet should have low resistance (see figure 4). it is also important to put c vcc , the bypass capacitor for the v cc pin, as close as possible between v cc and gnd. place c1 and c2 near the cpo and v in pins. surge sup- pressors, when used, should be mounted close to the ltc4353 using short lead lengths. 4353 f04 msop-16 w current flow via to ground plane s s s g d d d d m2 so-8 to load from supply b w current flow s s s g d d d d m1 so-8 to load from supply a c vcc track width w: 0.03 per ampere on 1oz cu foil drawing is not to scale! ltc4353
ltc 4353 11 4353f typical a pplica t ions 12v supply with capacitive reservoir for data backup on power fail for disk drive and solid-state drive applications 3.3v main and auxiliary supply diode-or (auxiliary ideal diode disabled if main above 2.95v) m1 si4126dy m2 si4126dy gate1 cpo1 cpo2 gnd en1 en2 4353 ta02 12v c vcc 0.1f storage device c1 56nf c2 56nf v in1 v cc onst1 onst2 out1 out2 gate2 v in2 ltc4353 r chrg 1k buck reg. c resv 3f c resv : 3 parallel strings, each with 3 series pm-5r0v305-r m1 si4126dy m2 si4126dy gate1 cpo1 cpo2 gnd en1 en2 4353 ta03 3.3v main 3.3v aux c vcc 0.1f out c1 56nf c2 56nf v in1 v cc onst1 onst2 out1 out2 gate2 v in2 ltc4353 r3 39.2k r4 10k
ltc 4353 12 4353f plug-in card supply holdup using ideal diode at 12v and 3.3v inputs plug-in card connectors backplane 4353 ta04 12v 3.3v m1 si4126dy m2 si4126dy gate1 cpo1 cpo2 c2 56nf nc v in1 out1 out2 gate2 v in2 ltc4353 c holdup1 3.3v out 12v out + c holdup2 + typical a pplica t ions
ltc 4353 13 4353f typical a pplica t ions redundant power supply system with oring on backplane, as in microtca load card 2 power supply module 1 4353 ta05 load card 1 12v si4126dy si4126dy gate1 cpo1 cpo2 gnd en1 en2 nc nc 0.1f v in1 v cc onst1 onst2 out1 out2 gate2 v in2 ltc4353 power supply module 2 12v si4126dy si4126dy gate1 cpo1 cpo2 gnd en1 en2 nc nc 0.1f v in1 v cc onst1 onst2 out1 out2 gate2 v in2 ltc4353
ltc 4353 14 4353f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?)
ltc 4353 15 4353f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?)
ltc 4353 16 4353f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0512 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1473/ltc1473l dual powerpath? switch driver n-channel, 4.75v to 30v/3.3v to 10v, ssop-16 package ltc1479 powerpath controller for dual battery systems three n-channel drivers, 6v to 28v, ssop-36 package ltc4352 low voltage ideal diode controller with monitoring n-channel, 0v to 18v, uv, ov, msop-12 and dfn-12 packages ltc4354 negative voltage diode-or controller and monitor dual n-channel, ?4.5v to ?80v, so-8 and dfn-8 packages ltc4355 positive high voltage ideal diode-or with supply and fuse monitors dual n-channel, 9v to 80v, so-16 and dfn-14 packages ltc4357 positive high voltage ideal diode controller n-channel, 9v to 80v, msop-8 and dfn-6 packages ltc4358 5a ideal diode internal n-channel, 9v to 26.5v, tssop-16 and dfn-14 packages LTC4370 tw o -supply diode-or current sharing controller dual n-channel, 0v to 18v, msop-16 and dfn-16 packages ltc4411 2.6a low loss ideal diode in thinsot? internal p-channel, 2.6v to 5.5v, 40a i q , sot-23 package ltc4412/ltc4412hv low loss powerpath controller in thinsot p-channel, 2.5v to 28v/36v, 11a i q , sot-23 package ltc4413/ltc4413-1 dual 2.6a, 2.5v to 5.5v, ideal diodes in dfn-10 dual internal p-channel, 2.5v to 5.5v, dfn-10 package ltc4414 36v low loss powerpath controller for large p -channel mosfet s p-channel, 3v to 36v, 30a i q , msop-8 package ltc4415 dual 4a ideal diodes with adjustable current limit dual p-channel 50m ideal diodes, 1.7v to 5.5v, 15mv forward drop, msop-16 and dfn-16 packages ltc4416/ltc4416-1 36v low loss dual powerpath controller for large p-channel mosfets dual p-channel, 3.6v to 36v, 70a i q , msop-10 package 1.2v ideal diode-or si4126dy si4126dy gate1 cpo1 cpo2 gnd en1 en2 4353 ta06 0.1f 5v to load 56nf 56nf v in1 v cc onst1 onst2 out1 out2 gate2 v in2 ltc4353 v ina 1.2v v inb 1.2v

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